Altera Arria GX Development Board - Manual (Page 21)

Altera Corporation Reference Manual 2–11
October 2007 Arria GX Development Board
Board Components
Flash Memory Configuration
A 512-Mb Spansion flash memory device is used to store configuration
files for the FPGA as well as any other necessary data. The target device
is a Spansion S29GL512N in a BGA package, which supports CFI flash
commands.
The flash memory map is determined by the MAX II CPLD design, which
is based on the Parallel Flash Loader (PFL) megafunction. The PFL
megafunction takes up to eight Quartus II programmer object files (.pof)
and stacks them into a single image to be written to flash memory using
the Quartus II Programmer and a USB-Blaster cable. This is done via the
JTAG header and the MAX II CPLD to flash memory.
Table 2–6 lists an example flash memory map. The sizes of various blocks
may change based on the settings used, such as the compression setting,
in the Quartus II Programmer. The PFL Option Bits are used by the
MAX II CPLD design to store the address of the POF files.
Table 2–6. Example Flash Memory Map
Memory Block Address
PFL option bits (Not negotiable in
address and size) 0x3FF0000
0x3FF0080
User space
(16MB-32MB) 0x03FF.FFEF
0x0200.0000
FPGA design 7 0x01FF.FFFF
0x01C0.0000
FPGA design 6 0x01BF.FFFF
0x0180.0000
FPGA design 5 0x017F.FFFF
0x0140.0000
FPGA design 4 0x013F.FFFF
0x0100.0000
FPGA design 3 0x00FF.FFFF
0x00C0.0000
FPGA design 2 0x00BF.FFFF
0x0080.0000
FPGA design 1 0x007F.FFFF
0x0040.0000
FPGA design 0 (default) 0x003F.FFFF
0x0000.0000