Altera Nios Development Board Stratix II Edition - Manual (Page 20)

2–10 Reference Manual Altera Corporation
Nios Development Board Stratix II Edition May 2007
Board Components
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A7 62 sdram_dq13
C7 63 sdram_dq14
D7 65 sdram_dq15
C9 16 sdram_dqs0
C6 51 sdram_dqs1
C10 20 sdram_dm0
B7 47 sdram_dm1
B10 29 sdram_a0
B9 30 sdram_a1
B8 31 sdram_a2
B6 32 sdram_a3
C5 35 sdram_a4
E11 36 sdram_a5
E10 37 sdram_a6
E9 38 sdram_a7
E8 39 sdram_a8
E7 40 sdram_a9
F11 28 sdram_a10
F10 41 sdram_a11
F8 42 sdram_a12
F10 26 sdram_ba0
G11 27 sdram_ba1
B3 22 sdram_cas_n
F13 44 sdram_cke
E12 24 sdram_cs_n
A3 23 sdram_ras_n
B4 21 sdram_we_n
C4 46 sdram_clk_n
C3 45 sdram_clk_p
Table 2–7. DDR SDRAM Pin Table (Continued)
FPGA Pin U63 Pin Board Net Name