Altera Nios Development Board Stratix II Edition - Manual (Page 47)

Altera Corporation Reference Manual 2–37
May 2007 Nios Development Board Stratix II Edition
Board Components
Nios II reference design is factory-programmed into the factory
configuration region of the flash memory. In addition, the FPGA can be
configured by the EPCS64 serial configuration device.
Configuration Process
At power-up or reset, the configuration controller attempts to configure
the FPGA with data from one of three sources, in the following order:
1. The EPCS64 serial configuration device
2. The user configuration from flash memory
3. The factory configuration from flash memory
First, the configuration controller puts the FPGA in active serial (AS)
configuration mode. The FPGA then attempts to read configuration data
from the EPCS64. If the FPGA finishes configuration successfully, the
configuration controller stops. If there is a valid configuration image
stored in the EPCS64, then the FPGA will only boot from the EPCS64 or
from the factory image of flash memory when the SW9 switch is
depressed. The user segment of EPCS64 will be ignored.
If configuration from the EPCS64 does not succeed, the configuration
controller puts the FPGA into passive serial (PS) mode and attempts to
load the user configuration from CFI flash memory (U5). If this also fails
(because the user configuration is either invalid or not present), the
configuration controller attempts to load the factory configuration from
flash memory.
When SW9 (Factory Config) is pressed, the configuration controller
ignores the user configuration and EPCS64, and configures the FPGA
with the factory configuration. SW9 provides an escape from a situation
in which a valid-but-nonfunctional design is present in user flash
memory or the EPCS64.
1 If the FPGA is configured in passive serial mode (such as when
it is configured from the CFI flash), the EPCS64 device is not
available to the FPGA after configuration.