DFI HU968 - Manual (Page 20)

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Chapter 3
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Signal Pin# Module Pin Type Pwr Rail /Tolerance HU968 Carrier Board Description
VGA_RED B89 O Analog Analog PD 150 to GND PD 150R,connect to VGA connector with EMI filter & ESD protect component. Red for monitor. Analog output
VGA_GRN B91 O Analog Analog PD 150 to GND PD 150R,connect to VGA connector with EMI filter & ESD protect component. Green for monitor. Analog output
VGA_BLU B92 O Analog Analog PD 150 to GND PD 150R,connect to VGA connector with EMI filter & ESD protect component. Blue for monitor. Analog output
VGA_HSYNC B93 O CMOS 3.3V / 3.3V Connect to VGA connector with a3.3V Buffer IC to isolate PCH & Display Device Horizontal sync output to VGA monitor
VGA_VSYNC B94 O CMOS 3.3V / 3.3V Connect to VGA connector with a 33V Buffer IC to isolate PCH & Display Device Vertical sync output to VGA monitor
VGA_I2C_CK B95 I/O OD CMOS 3.3V / 3.3V PU 2.2K to 3.3V Connect to VGA connector with a 3.3V to 5V Level shift circuit. DDC clock line (I2C port dedicated to identify VGA monitor capabilities)
VGA_I2C_DAT B96 I/O OD CMOS 3.3V / 3.3V PU 2.2K to 3.3V Connect to VGA connector with a 3.3V to 5V Level shift circuit. DDC data line.
Signal Pin# Module Pin Type Pwr Rail /Tolerance HU968 Carrier Board Description
SER0_TX A98 O CMOS 3.3V/5V PD 4.7K to GND General purpose serial port 0 transmitter
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
SER0_RX A99 I CMOS 3.3V/5V PU 47K to 3.3V
General purpose serial port 0 receiver
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
SER1_TX A101 O CMOS 3.3V/5V PD 4.7K to GND General purpose serial port 1 transmitter
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
SER1_RX A102 I CMOS 3.3V/5V PU 47K to 3.3V General purpose serial port 1 receiver
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
Signal Pin# Module Pin Type Pwr Rail /Tolerance HU968 Carrier Board Description
I2C_CK B33 I/O OD CMOS 3.3V Suspend/3.3V PU 2.2K to 3V3_DU_EC General purpose I2C port clock output
I2C_DAT B34 I/O OD CMOS 3.3V Suspend/3.3V PU 2.2K to 3V3_DU_EC General purpose I2C port data I/O line
SPKR B32 O CMOS 3.3V / 3.3V
Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.
WDT B27 O CMOS 3.3V / 3.3V Output indicating that a watchdog time-out event has occurred.
FAN_PWNOUT B101 O OD CMOS 3.3V / 3.3V Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
FAN_TACHIN B102 I OD CMOS 3.3V / 3.3V PU 10K to 3V3 Fan tachometer input for a fan with a two pulse output.
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
TPM_PP A96 I CMOS 3.3V / 3.3V
Trusted Platform Module (TPM) Physical Presence pin. Active high.
TPM chip has an internal pull down. This signal is used to indicate
Physical Presence to the TPM.
Signal Pin# Module Pin Type Pwr Rail /Tolerance HU968 Carrier Board Description
PWRBTN# B12 I CMOS 3.3V Suspend/3.3V PU 10K to 3V3_DU_EC PU 4.7K to 3V3_SB
A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.
SYS_RESET# B49 I CMOS 3.3V Suspend/3.3V PU 10K to 3V3_DU NC PU 4.7K to 3V3_SB
Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.
CB_RESET# B50 O CMOS 3.3V Suspend/3.3V PD 100K to GND
Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.
PWR_OK B24 I CMOS 3.3V / 3.3V PU 10K to 3V3
Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.
SUS_STAT# B18 O CMOS 3.3V Suspend/3.3V Indicates imminent suspend operation; used to notify LPC devices.
SUS_S3# A15 O CMOS 3.3V Suspend/3.3V PD 100K to GND
Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.
SUS_S4# A18 O CMOS 3.3V Suspend/3.3V PD 100K to GND Indicates system is in Suspend to Disk state. Active low output.
SUS_S5# A24 O CMOS 3.3V Suspend/3.3V PD 100K to GND Indicates system is in Soft Off state.
WAKE0# B66 I CMOS 3.3V Suspend/3.3V PU 10K to 3V3_DU PCI Express wake up signal.
WAKE1# B67 I CMOS 3.3V Suspend/3.3V NA General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.
BATLOW# A27 I CMOS 3.3V Suspend/ 3.3V PU 10K to 3V3_DU
Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.
LID# A103 I OD CMOS 3.3V Suspend/12V PU 10K to 3V3_DU_EC LID switch. Low active signal used by the ACPI operating system for a LID switch.
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
SLEEP# B103 I OD CMOS 3.3V Suspend/12V PU 10K to 3V3_DU
Sleep button. Low active signal used by the ACPI operating system to bring the
system to sleep state or to wake it up again.
(Recommend add Protecting Logic Level Signals on Pins Reclaimed from VCC_12V)
Power and System Management Signals Descriptions
VGA Signals Descriptions
Serial Interface Signals Descriptions
Miscellaneous Signal Descriptions