Grass Valley PDR 200 Service Manual - Manual (Page 45)

Slave Enhanced Disk Recorder
PDR200 Service Manual 3-13
Clocks
Clock generation for the EDR boards and for other GPCI bus capable boards is done
on the master EDR board using a 33.333 Mhz clock oscillator chip and a set of PLL
clock chips. The PLL clock chips provide multiple clock outputs that are phase locked
to the oscillator frequency. In addition the PLL chips provide a 2x version of the clock
which is used by the RTP and the JPEG memory controllers.
One of two PLL chips on the master EDR provides local clocks which are distributed
to on-board logic. The second PLL chip provides individual clocks which are routed
through the GPCI connector to the PCI_IC board. The PCI_IC board then routes a
clock line to each of the GPCI slots. For slave EDR boards, this clock is then used by
its PLL clock chips to provide phase locked clocks for its on-board logic. This method
of clock distribution provides a very low skew between all of the GPCI interface logic
resulting in a more robust design.
Slave Enhanced Disk Recorder
The Slave Enhanced Disk Recorder (SEDR) board uses the same circuit board as the
MEDR, but is only loaded with the components needed to implement the EISA, LPCI,
JPEG, SCSI, and GPCI interfaces. Since board routing is the same, each EDR board
generates a Master/Slave signal. Where a pull-up generates the signal on a Master
EDR, a pull-down resistor generates it on a Slave EDR. For the MEDR board, this
signal is what enables it to handle GPCI interrupts and arbitration.
This same signal is connected to the EISA configuration PLD and is used to present
the corresponding Master or Slave EISA ID value when the EISA ID register is
accessed. On a SEDR board, the GPCI bus clock through the PLL clock generates the
PCI bus clocks.
PCI Board
A Profile configuration with one MEDR board, one SEDR board, and one Fibre
Channel board uses a three connector PCI board. This board has one unique connector
(labelled MASTER) which must be connected to the MEDR board. The other
connectors have identical signal connections, except for the generation of their
G_IDSEL signal. To configure the PCI interfaces to components on the boards that
connect to the GPCI bus, the GPCI address lines are connected through a resistor to
the G_IDSEL signal for a connector.
Note that connectors are always referenced by the MASTER connector on the PCI
board. Also note that the PCI board does not route the VCC_NC signals between
connectors, but these signals are connected to the VCC plane on each of the boards to
provide a good signal impedance characteristic.