Chapter 14 timing diagrams, Figure 14.1 asynchronous cycle - nads=0, Datasheet – SMSC LAN91C111 User Manual
Page 110
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10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08)
110
SMSC LAN91C111 REV C
DATASHEET
Chapter 14 Timing Diagrams
Figure 14.1 Asynchronous Cycle - nADS=0
PARAMETER
MIN
TYP
MAX
UNITS
t1
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
2
ns
t2
A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming
nADS Tied Low)
5
ns
t3
nRD Low to Valid Data
15
ns
t4
nRD High to Data Invalid
2
15
ns
t5
Data Setup to nWR Inactive
10
ns
t5A
Data Hold After nWR Inactive
5
ns
t6
nRD Strobe Width
15
ns
t5A
t5
t1
t4
t3
t2
t6
t6
Valid
Valid
Valid
Address, AEN, nBE[3:0]
nADS
Read Data
nRD, nWR
Write Data
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