SMSC LAN91C111 - Manual (Page 85)

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 85 Revision 1.91 (08-18-08)
DATASHEET
10.2 Typical Flow of Events for Transmit (Auto Release = 0)
Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode
S/W DRIVER CONTROLLER FUNCTION
1 Write and set (1) the “EPH Power EN” Bit, located in
the configuration register, Bank 1 Offset 0.
2 Ethernet MAC Enables the RX Clock, TX clock
derived from the Internal PHY. The EPH Clock is
also enabled.
3 Write the PDN bit in PHY MI Register 0 to 0 The PHY is then set in isolation mode (MII_DIS bit
is set). Need to clear this MII_DIS bit; and, need to
wait for 500 ms for the PHY to restore normal.
4 Internal PHY entered normal operation mode
5 Issue MMU Reset Command
6 Restore Device Register Level Context.
7 Enable Transmitter – Set the TXENA bit of the
Transmit Control Register Ethernet MAC can now transmit Ethernet Packets.
8 Enable Receiver – Set (1) the RXEN bit of the
Receive Control Register. Ethernet MAC is now able to receive Packets.
9 Ethernet MAC is now restored for normal operation.
S/W DRIVER MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES -
the MMU attempts to allocate N bytes of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION CODE -
Poll until the ALLOC INT bit is set or enable its mask
bit and wait for the interrupt. The TX packet number
is now at the Allocation Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write the
Pointer Register, then use a block move operation
from the upper layer transmit queue into the Data
Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"
- This command writes the number present in the
Packet Number Register into the TX FIFO. The
transmission is now enqueued. No further CPU
intervention is needed until a transmit interrupt is
generated.
5 The enqueued packet will be transferred to the MAC
block as a function of TXENA (nTCR) bit and of the
deferral process (1/2 duplex mode only) state.