SMSC LAN91C111 - Manual (Page 72)

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08) 72 SMSC LAN91C111 REV C
DATASHEET
REGAD[4:0] Register
Address If REGAD[4:0] = 00000-11110, these bits determine the specific
register from which D[15:0] is read/written. If multiple register access
is enabled and REGAD[4:0] = 11111, all registers are read/written in
a single cycle. W
TA1
TA0 Turnaround
Time These bits provide some turnaround time for MDIO
When READ = 1, TA[1:0] = Z0
When WRITE = 1, TA[1:0] = 10
The turnaround time is a 2 bit time spacing between the Register
Address field and the Data field of a management frame to avoid
contention during a read transaction. For a read transaction, both the
STA and the PHY shall remain in a high impedance state for the first
bit time of the turnaround. The PHY shall drive a zero bit during the
second bit time of the turnaround of a read transaction. During a
write transaction, the STA shall drive a one bit for the first bit time of
the turnaround and a zero bit for the second bit time of the
turnaround.
R/W
D[15:0].... Data These 16 bits contain data to/from one of the eleven registers
selected by register address bits REGAD[4:0]. Any
SYMBOL NAME DEFINITION R/W