SMSC LAN91C111 - Manual (Page 48)

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08) 48 SMSC LAN91C111 REV C
DATASHEET
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set
and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the
FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on
the line. If a packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal
operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA
to 0. In order to force another collision, TXENA must be set to 1 again.
LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the
PHY chip in loopback mode.
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the
LAN91C111 will complete the current transmission before stopping. When stopping due to an error,
this bit is automatically cleared.
8.6 Bank 0 - EPH Status Register
This register stores the status of the last transmitted frame. This register value, upon individual
transmit packet completion, is stored as the first word in the memory area allocated to the packet.
Packet interrupt processing should use the copy in memory as the register itself will be updated by
subsequent packet transmissions. The register can be used for real time values (like TXENA and LINK
OK). If TXENA is cleared the register holds the last packet completion status.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A
transition on the value of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count
(15). Cleared by reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2
byte times. Cleared at the end of every packet sent.
LOST_CARR - Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than
64 byte times into the frame). When detected the transmitter jams and turns itself off clearing the
TXENA bit in TCR. Cleared by setting TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4
μs of the inter frame
gap. Cleared at the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of
every transmit frame.
OFFSET NAME TYPE SYMBOL
2 EPH STATUS REGISTER READ ONLY EPHSR
HIGH
BYTE
Reserved LINK_
OK
Reserved CTR
_ROL
EXC
_DEF
LOST
CARR
LATCOL Reserved
0 -nLNK pin 0 0 0 0 0 0
LOW
BYTE
TX
DEFR
LTX
BRD
SQET 16COL LTX
MULT
MUL
COL SNGL
COL
TX_SUC
0 0 0 0 0 0 0 0