9 register 19. mask - structure and bit definition, Register 19. mask - structure and bit definition, Datasheet – SMSC LAN91C111 User Manual

Page 81

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

SMSC LAN91C111 REV C

81

Revision 1.91 (08-18-08)

DATASHEET

9.9

Register 19. Mask - Structure and Bit Definition

SSD:

Start Of Stream Error

1 = No Start Of
Stream Delimiter
Detected on Receive
Data

0 = Normal

ESD:

End Of Stream Error

1 = No End Of
Stream Delimiter
Detected on Receive
Data

0 = Normal

RPOL:

Reverse Polarity
Detect

1 = Reverse Polarity
Detected

JAB:

Jabber Detect

1 = Jabber Detected

0 = Normal

SPDDET:

100/10 Speed Detect

1 = Device in
100Mbps Mode
(100BASE-TX)

0 = Device in
10Mbps Mode
(10BASE-T)

DPLXDET:

Duplex Detect

1 = Device In Full
Duplex

0 = Device In Half
Duplex

Reserved:

Reserved

Reserved for Factory
Use

MINT

MLNKFAIL

MLOSSSYN

MCWRD

MSSD

MESD

MRPOL

MJAB

RW

RW

RW

RW

RW

RW

RW

RW

1

1

1

1

1

1

1

1

MSPDDT

MDPLDT

Reserved

Reserved Reserved

Reserved

Reserved

Reserved

RW

RW

RW

RW RW

RW

RW

RW

1

1

0

0

0

0

0

0

MINT:

Interrupt Mask
Interrupt Detect

1 = Mask Interrupt
For INT In Register
18

0 = No Mask

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