Datasheet – SMSC LAN91C111 User Manual
Page 52
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.91 (08-18-08)
52
SMSC LAN91C111 REV C
DATASHEET
Register) and determine the duplex mode. When this bit is set (1), the Internal PHY will operate at
full duplex mode. When this bit is cleared (0), the Internal PHY will operate at half Duplex mode. When
the ANEG bit = 1, this bit is ignored and duplex mode is determined by the outcome of the Auto-
negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register) when the
ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG
bit and the ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits
is cleared (0), the PHY is placed in manual mode.
WHAT DO YOU
WANT TO DO?
AUTO-
NEGOTIATION
CONTROL BITS
AUTO-NEGOTIATION ADVERTISEMENT
REGISTER
DUPLEX
MODE
CONTROL
FOR THE
MAC
Try to Auto-Negotiate
to ……
ANEG
Bit
ANEG_E
N
Bit
TX_FDX
Bit
TX_HDX
Bit
10_FDX
Bit
10_HDX
Bit
SWFDUP
Bit
RPCR
(MAC)
Register 0
(PHY)
Register
4
(PHY)
Register
4
(PHY)
Register
4
(PHY)
Register
4
(PHY)
Transmit
Control
Register
(MAC)
100 Full Duplex
1
1
1
1
1
1
1
100 Half Duplex
1
1
0
1
1
1
0
10 Full Duplex
1
1
0
0
1
1
1
10 Half Duplex
1
1
0
0
0
1
0
WHAT DO YOU
WANT TO DO?
AUTO-NEGOTIATION
CONTROL BITS
SPEED AND DUPLEX MODE CONTROL
FOR THE PHY
DUPLEX
MODE
CONTROL
FOR THE
MAC
Try to Manually Set to
……
ANEG
Bit
ANEG_E
N
Bit
SPEED
Bit
DPLX
Bit
SPEED
Bit
DPLX
Bit
SWFDUP
Bit
RPCR
(MAC
Bank 0
Offset A)
Register 0
(PHY)
RPCR
(MAC
Bank 0
Offset A)
RPCR
(MAC
Bank 0
Offset A)
Register
0
(PHY)
Register
0
(PHY)
Transmit
Control
Register
(MAC)
100 Full Duplex
0
0
1
1
X
X
1
0
1
1
1
X
X
1
1
0
X
X
1
1
1
100 Half Duplex
0
0
1
0
X
X
0
0
1
1
0
X
X
0
1
0
X
X
1
0
0