NEC PD78058FY(A) - Manual (Page 234)

234
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS
(3) Operation as a Square Wave Output
Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor
registers 10 and 20 (CR10, CR20) as the interval. When setting the count value, the value of the upper 8
bits is set in CR20 and the value of the lower 8 bits is set in CR10.
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting
bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected
frequency to be output.
Table 9-10. Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width Maximum Pulse Width Resolution
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
2
×
1/f X 2 2 ×
1/f X 2 17 ×
1/f X 2 18 ×
1/f X 2
×
1/f X 2 2 ×
1/f X
(400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns)
2 2 ×
1/f X 2 3 ×
1/f X 2 18 ×
1/f X 2 19 ×
1/f X 2 2 ×
1/f X 2 3 ×
1/f X
(800 ns) (1.6
µ
s) (52.4 ms) (104.9 ms) (800 ns) (1.6
µ
s)
2 3 ×
1/f
X
2 4 ×
1/f
X
2 19 ×
1/f
X
2 20 ×
1/f
X
2 3 ×
1/f
X
2 4 ×
1/f
X
(1.6
µ
s) (3.2
µ
s) (104.9 ms) (209.7 ms) (1.6
µ
s) (3.2
µ
s)
2 4 ×
1/f
X
2 5 ×
1/f
X
2 20 ×
1/f
X
2 21 ×
1/f
X
2 4 ×
1/f
X
2 5 ×
1/f
X
(3.2
µ
s) (6.4
µ
s) (209.7 ms) (419.4 ms) (3.2
µ
s) (6.4
µ
s)
2 5 ×
1/f
X
2 6 ×
1/f
X
2 21 ×
1/f
X
2 22 ×
1/f
X
2 5 ×
1/f
X
2 6 ×
1/f
X
(6.4
µ
s) (12.8
µ
s) (419.4 ms) (838.9 ms) (6.4
µ
s) (12.8
µ
s)
2 6 ×
1/f X 2 7 ×
1/f X 2 22 ×
1/f X 2 23 ×
1/f X 2 6 ×
1/f X 2 7 ×
1/f X
(12.8
µ
s) (25.6
µ
s) (838.9 ms) (1.7 s) (12.8
µ
s) (25.6
µ
s)
2 7 ×
1/f X 2 8 ×
1/f X 2 23 ×
1/f X 2 24 ×
1/f X 2 7 ×
1/f X 2 8 ×
1/f X
(25.6
µ
s) (51.2
µ
s) (1.7 s) (3.4 s) (25.6
µ
s) (51.2
µ
s)
2 8 ×
1/f X 2 9 ×
1/f X 2 24 ×
1/f X 2 25 ×
1/f X 2 8 ×
1/f X 2 9 ×
1/f X
(51.2
µ
s) (102.4
µ
s) (3.4 s) (6.7 s) (51.2
µ
s) (102.4
µ
s)
2 9 ×
1/f X 2 10 ×
1/f X 2 25 ×
1/f X 2 26 ×
1/f X 2 9 ×
1/f X 2 10 ×
1/f X
(102.4
µ
s) (204.8
µ
s) (6.7 s) (13.4 s) (102.4
µ
s) (204.8
µ
s)
2 11 ×
1/f X 2 12 ×
1/f X 2 27 ×
1/f X 2 28 ×
1/f X 2 11 ×
1/f X 2 12 ×
1/f X
(409.6
µ
s) (819.2
µ
s) (26.8 s) (53.7 s) (409.6
µ
s) (819.2
µ
s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Bit 0 of oscillation mode selection register (OSMS)
3. Values in parentheses when operated at f X = 5.0 MHz.