NEC PD78058FY(A) User Manual
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78058F SUBSERIES)
(10) How to determine the slave busy state
When a device is in the master mode, use the following procedure to determine if the slave is in the busy state
or not.
<1> Detect the generation of an acknowledge signal (ACK) or interrupt request signal.
<2> Set the port mode register PM25 (or PM26) of pin SB0/P25 (or SB1/P26) in the input mode.
<3> Read the terminal’s status (the pin is in the ready state if it is in the high level).
After detecting the ready state, set 0 in the port mode register and return to the output mode.
(11) SBI mode precautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) In SBI, after specifying reset of BUSY, the BUSY signal is output until the fall of the next serial clock. If
WUP = 1 is set during this interval by mistake, it will be impossible to reset BUSY. Therefore, after resetting
the BUSY signal, confirm that the level of the SB0 (SB1) pin has gone high before setting WUP to “1”.
(d) For pins that are to be used for data input/output, be sure to carry out the following settings before serial
transfer of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
(e) When the SCK0 line is high level and the SB0 (SB1) line changes from low level to high level, or from
high level to low level, this is recognized as a bus release signal or command signal. Therefore, if there
are shifts in the bus change timing due to influences such as the board capacity, this may be judged to
be a bus release signal (or command signal) even though data is being sent. Thus, much care should
be taken in wiring.