NEC PD78058FY(A) - Manual (Page 386)

386
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
µ
PD78058FY SUBSERIES)
CLC (manipulated by bit manipulation instruction)
Wait request signal
Serial clock (low while transfer is stopped) SCL
Figure 17-29. Logic Circuit of SCL Signal
Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit.
2. CLC: Bit 3 of interrupt timing specify register (SINT)