Toshiba, 3 tripped status monitoring, Read/write – Toshiba Q-Flowsaver II User Manual

Page 39

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TOSHIBA

8.3

Tripped Status Monitoring

Tripped status monitoring displays abnormal status conditions that can occur during

normal inverter operation. The table below shows these abnormal conditions which will

cause the inverter to trip "off" (stop normal operations). They are usually caused by

excessive power dissipation in either the inverter or motor, or by other circuit

abnormalities. A tripped status monitoring display usually appears during the time that

the abnormal condition is occurring and then remains on the display after the inverter

trips off. The inverter will remain off and the tripped status will remain displayed until the

inverter is attended to (reset) by the operator. Most conditions, which cause the inverter

to trip, occur very rapidly and the operator usually will not be aware that the trip

conditions are in process until the inverter has stopped. Each of the trip statuses are

automatically recorded in the non-volatile EEPROM memory of the inverter. An ordered

semi-permanent record of each trip (up to four) is created and can be viewed during the

normal status monitoring "scroll". These recorded trips are viewed immediately after the

keypad's software version, in the order that they occurred, as the

READ/WRITE

key is

pressed. These trips remain in the memory until replaced by new trips.

Key

Display

Status Condition

n r

I

U

L

I

Overcurrent occurred during an acceleration.

I l l

_/

u i _ i _

Overcurrent occurred during a deceleration.

I l l _ i

U

L _/

Overcurrent occurred during a run.

I l l u

U

L / (

Overcurrent detected at start-up (suspect inverter damage).

n r I

U

L L

Overcurrent detected at start-up (suspect load short circuit).

I I u

_/

U I

/_

Overvoltage generated during deceleration.

I I u

U I

Overvoltage from power supply.

n I

U

L

Overload of motor occurred.

n u

U I I

Overheat of inverter body or external fault occurred.

L L

L I

Ground fault overcurrent occurred in the load circuit.

- I I

.

1

-

Main RAM in main CPU is abnormal.

- I I . - I

Main ROM in main CPU is abnormal.

u

I I . I

RAM in operating panel CPU is abnormal.

I I . u

ROM in operating panel CPU is abnormal.

I I .1-1

Key in the operating panel keypad defective.

L LI

L I

EEPROM data abnormality.

L U -I

L I I-

EEPROM trip data abnormality.

L LI -I

L I -I

EEPROM setting data abnormality.

I / . L

Communication data link abnormality.

These faults can be programmed to automatically restart

8 - 3

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