ADLINK PCIe-7300A - Manual (Page 112)

102 Appendix
The gate input when low, will force the output high. When the
gate input goes high, the counter will start form the initial count.
Thus, the gate input can be used to synchronized by software.
When this mode is set, the output will remain high until after the
count register is loaded. The output then can also be synchro-
nized by software.
Mode 3: Square Wave Rate Generator.
Similar to MODE 2 except that the output will remain high until
one half the count has been completed (or even numbers) and
go low for the other half of the count. This is accomplished by
decrement the counter by two on the falling edge of each clock
pulse. When the counter reaches terminal count, the state of
the output is changed and the counter is reloaded with the full
count and the whole process is repeated.
If the count is odd and the output is high, the first clock pulse
(after the count is loaded) decrements the count by 1. Subse-
quent clock pulses decrement the clock by 2 after time-out, the
output goes low and the full count is reloaded. The first clock
pulse (following the reload) decrements the counter by 3. Sub-
sequent clock pulses decrement the count by 2 until time-out.
Then the whole process is repeated. In this way, if the count is
odd, the output will be high for (N + 1)/2 counts and low for (N -
1)/2 counts.
In Modes 2 and 3, if a CLK source other then the system clock
is used, GATE should be pulsed immediately following Way
Rate of a new count value.
Mode 4: Software Triggered Strobe.
After the mode is set, the output will be high. When the count is
loaded, the counter will begin counting. On terminal count, the
output will go low for one input clock period, then will go high
again.
If the count register is reloaded during counting, the new count
will be loaded on the next CLK pulse. The count will be inhib-
ited while the GATE input is low.