ADLINK PCIe-7300A - Manual (Page 69)

Operation Theory 59
4.11.4 Pattern Generator
The digital data is output to the peripheral device periodically
based on the clock signals occur at a constant rate. The digital
pattern are stored in the cPCI/PCI/PCIe-7300A’s on-board FIFO
with the length of pattern less than or equal to 16K samples.
The operations sequence of pattern generator are listed:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit
data width.
2. Enable or disable the active terminators.
3. Define the output timer pacer rate to be 20MHz, 10MHz,
or the output 82C54 timer 1. The timer pacer controls the
output rate.
4. Set the output patterns into the output FIFO by direct
FIFO access
5. Start the pattern generator function.
6. The pattern generator function will not stop until users
stop the process