ADLINK PCIe-7300A - Manual (Page 89)

C/C++ Libraries 79
transfers are always longwords, this is 2 million long-
words (2^21).
3. After the input sampling is started, the input data is
stored in the FIFO of PCI controller. Each bus mastering
data transfer continually tests if any data in the FIFO and
then blocks transfer, the system will continuously loop
until the conditions are satisfied again but will not exit the
block transfer cycle if the block count is not complete. If
there is momentarily no input data, the cPCI/PCI/PCIe-
7300A will relinquish the bus temporarily but returns
immediately when more input data appear. This opera-
tion continues until the whole block is done.
4. This operation proceeds transparently until the PCI con-
troller transfer byte count is reached. All normal PCI bus
operation applies here such as a receiver which cannot
accept the transfers, higher priority devices requesting
the PCI bus, etc. Remember that only one PCI initiator
can have bus mastering at any one time. However,
review the PCI priority and "fairness" rules. Also study
the effects of the Latency Timer. And be aware that the
PCI priority strategy (round robin rotated, fixed priority,
custom, etc.) is unique to your host PC and is explicitly
not defined by the PCI standard. You must determine
this priority scheme for your own PC (or replace it).
5. The interrupt request from the PCI controller can be
optionally set up to indicate that this longword count is
complete although this can also be determined by polling
the PCI controller.
@ Syntax
Visual C/C++ (Windows 95)
int W_7300_DI_DMA_Start (int card_number, HANDLE
memID, U32 count, int clear_fifo, int
disable_di)
Visual Basic (Windows 95)
W_7300_DI_DMA_Start (ByVal card_number As Long,
ByVal memID As Long, ByVal count As Long,