ADLINK PCIe-7300A - Manual (Page 59)

Operation Theory 49
Figure 4-8: DIREQ as input data strobe (Falling Edge Active)
Note: From the timing diagram of external clock mode, the maxi-
mum frequency can be up to 40MHz. However, users should
note that when the sampling frequency of digital input is
higher than the PCI bus bandwidth (33Mhz), or the band-
width of chipset (30Mhz typically) from PCI bus to system
memory. Users should check the overrun status when the
DMA block size is larger than 16K samples. If overrun al-
ways happens, users should reduce the DMA block size or
slow down the sampling frequency. For example, the DMA
block size should be smaller than 64K when the external
clock is 40Mhz in the DOS Operation
4.10.3 Digital Input DMA in Handshaking Mode
For digital input, through DI-REQ input signal and DI-ACK output
signal, the digital input can have simple handshaking data trans-