ADLINK PCIe-7300A - Manual (Page 48)

38 Operation Theory
4.5 Bus-mastering DMA
Digital I/O data transfer between cPCI/PCI/PCIe-7300A and PC’s
system memory is through bus mastering DMA, which is con-
trolled by PCI bridge chip PLX PCI-9080. The PCI bus master
means the device requires fast access to the bus or high data
throughput in order to achieve good performance.
However, users should note that when more than one bus masters
request the bus ownership, all masters will share the bandwidth of
PCI bus and the performance of each master will unavoidably
drop. Therefore, in order to obtain the maximum data throughput
of the cPCI/PCI/PCIe-7300A, it is recommended to remove or dis-
able the bus mastering function of other bus masters, such as net-
work, SCSI, modem adapters, and so on.
The maximum data throughput of the cPCI/PCI/PCIe-7300A is
also limited by the data throughput of the bridge chipset (North
Bridge: NB) between PCI bus and system memory. The typical
data throughput of NB chipset is 120MB/s for input and 100MB/s
for output. Please refer to the Figure 4-6. User should check the
specs of the chipset on your main-board to determine the cPCI/
PCI/PCIe-7300A‘s maximum data throughput. The 80MB/s data
throughput of the cPCI/PCI/PCIe-7300A is guaranteed in the per-
vious system setup by using the internal 20MHz-sampling rate.
Figure 4-4: Maximum data throughput
From Figure 4-6, we can find that NB chipset is the bottleneck of
the maximum data transfer rate as only one bus master exists.
When the transfer rate users required is smaller than the maxi-
mum transfer rate, by using scatter/gather (see 4.6), users can
transfer the maximum data size as they have on their system
memory. However, if the data should be real-time saved to the
PCI/PCIe/cPCI-7300A