ADLINK PCIe-7300A - Manual (Page 55)

Operation Theory 45
4.10 Digital Input Operation Mode
4.10.1 Digital Input DMA in Internal Clock Mode
There are three sources to trigger digital input in the internal clock
mode: 20MHz, 10MHz, and programmable timer 82C54. There
are three counters in 82C54, where the counter 0 is used for sam-
pling clock source for digital input. The operations sequence of
digital input with internal clock are listed as follows:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit
data width.
2. Enable or disable the active terminators.
3. Define the input sampling rate to be 20MHz, 10MHz, or
the output of 82C54 counter 0.
4. Define the starting mode to be NoWait or WaitTRIG.
5. The digital input data are stored in the input FIFO after a
DI command is issued and waiting for DI-TRIG signal if
in WaitTRIG mode.
6. The data in the input FIFO will be transferred into system
memory directly and automatically by bus mastering
DMA.