Altera Avalon Verification IP Suite - Manual (Page 118)

event_src_ready()
event_src_ready()
Prototype:
Verilog HDL: N.A.
VHDL: bfm_id
Arguments:
void
Returns:
Notifies the testbench that the ready signal was asserted. Description:
VHDL Language support:
event_src_transaction_complete()
event_src_transaction_complete()
Prototype:
Verilog HDL: N.A.
VHDL:
bfm_id
Arguments:
void Returns:
Notifies the testbench that all transactions were accepted. Description:
VHDL Language support:
get_response_latency()
get_response_latency()
Prototype:
Verilog HDL: None
VHDL: response_latency , bfm_id , req_if(bfm_id)
Arguments:
int Returns:
Returns the response latency in cycles due to back pressure for the most recently
removed transaction. Description:
Verilog HDL, VHDL Language support:
Avalon-ST Source BFM Altera Corporation
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event_src_ready() 8-6