Altera Avalon Verification IP Suite - Manual (Page 48)

signal_read_response_complete
signal_read_response_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the read response has been received and inserted into the response
queue. Description:
Verilog HDL Language support:
signal_response_complete
signal_response_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Triggers when either
signal_read_response_complete
or
signal_write_
response_complete is triggered.
Description:
Verilog HDL Language support:
signal_write_response_complete
signal_write_response_complete
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the write response has been received and inserted into the response
queue. Description:
Verilog HDL Language support:
Avalon-MM Master BFM Altera Corporation
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