Altera Avalon Verification IP Suite - Manual (Page 125)

signal_response_done
signal_response_done
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the response to a driven data beat is available. Description:
Verilog HDL Language support:
signal_src_driving_transaction
signal_src_driving_transaction
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals when the source begins to drive a transaction to the interface. Description:
Verilog HDL Language support:
signal_src_not_ready
signal_src_not_ready
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that the
ready
signal is not asserted. Description:
Verilog HDL Language support:
signal_src_ready
signal_src_ready
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the ready signal is asserted. Description:
Verilog HDL Language support:
Altera Corporation Avalon-ST Source BFM
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8-13 signal_response_done