Altera Avalon Verification IP Suite - Manual (Page 168)

signal_grant_deasserted_while_request_remain_asserted
signal_grant_deasserted_while_request_remain_asserted
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
None. Arguments:
void
Returns:
Triggers when the grant signal changes value from high to low while the request
signal remains asserted. Description:
Verilog HDL Language support:
signal_interface_granted
signal_interface_granted Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
None. Arguments:
void
Returns:
Triggers when the grant signal is asserted. Description:
Verilog HDL Language support:
signal_max_transaction_queue_size
signal_max_transaction_queue_size Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
None. Arguments:
void
Returns:
Triggers when the size of the pending queue exceeds the maximum size. Description:
Verilog HDL Language support:
Altera Corporation Tri-State Conduit BFM
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12-9 signal_grant_deasserted_while_request_remain_asserted