Altera Avalon Verification IP Suite - Manual (Page 181)

get_result_delay()
int get_result_delay() Prototype:
Verilog HDL: None
VHDL: result_delay , bfm_id , req_if(bfm_id)
Arguments:
Width of the data
(ci_data_t)
that can contain the following variables:
•
[Word_width-1:0]
• [Ext_width-1:0]
• [Addr_width-1:0]
Returns:
Returns the result delay. Description:
Verilog HDL, VHDL Language support:
get_result_queue_size()
int get_result_queue_size(int size)
Prototype:
Verilog HDL: None
VHDL:
result_queue_size
,
bfm_id
,
req_if(bfm_id)
Arguments:
int size . Returns:
Returns the number of results in the queue. Description:
Verilog HDL, VHDL Language support:
get_result_value()
string get_result_value()
Prototype:
Verilog HDL: None
VHDL:
result_value
,
bfm_id
,
req_if(bfm_id)
Arguments:
Width of the data (ci_data_t) that can contain the following variables:
• [Word_width-1:0]
•
Ext_width-1:0]
•
[Addr_width-1:0]
Returns:
Returns the instruction result. Description:
Verilog HDL, VHDL Language support:
Nios II Custom Instruction Master BFM Altera Corporation
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get_result_delay() 14-6