Altera Avalon Verification IP Suite - Manual (Page 158)

event_reset_asserted
event_reset_asserted Prototype:
Verilog HDL: N.A.
VHDL: None
Arguments:
void Returns:
Notifies the testbench that reset has been asserted. Description:
VHDL Language support:
get_<role name>()
int <role name port width> get_<role name>()
Prototype:
Verilog HDL: None
VHDL:
value
Arguments:
value
Returns:
Returns interface signal value from the input/bidirectional port. Description:
Verilog HDL, VHDL Language support:
get_version()
string get_version() Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
string
Returns:
Returns BFM version as a string of three integers separated by periods. For example,
version 13.1 sp1 is encoded as "13.1.1". Description:
Verilog HDL Language support:
Altera Corporation Conduit BFM
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11-3 event_reset_asserted