Altera Avalon Verification IP Suite - Manual (Page 132)

get_transaction_idles()
get_transaction_idles()
Prototype:
Verilog HDL: None
VHDL: transaction_idles , bfm_id , req_if(bfm_id)
Arguments:
bit[31:0]
Returns:
Returns the number of idle cycles in the most recently removed transaction. Description:
Verilog HDL, VHDL Language support:
get_transaction_eop()
get_transaction_eop()
Prototype:
Verilog HDL: None
VHDL:
transaction_eop
,
bfm_id
,
req_if(bfm_id)
Arguments:
bit Returns:
Returns the transaction end of packet status in the most recently removed
transaction. Description:
Verilog HDL, VHDL Language support:
get_transaction_empty()
get_transaction_empty()
Prototype:
Verilog HDL: None
VHDL:
transaction_empty
,
bfm_id
,
req_if(bfm_id)
Arguments:
STEmpty_t Returns:
Returns the number of empty symbols in the most recently removed transaction. Description:
Verilog HDL, VHDL Language support:
Avalon-ST Sink BFM Altera Corporation
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get_transaction_idles() 9-6