Altera Avalon Verification IP Suite - Manual (Page 159)

set_<role name>()
void set_<role name>()
Prototype:
Verilog HDL: new_value
VHDL: new_value
Arguments:
void
Returns:
Rewrites the registers inside the BFMs that are driven to the
<role name>
output
ports.
Description:
Verilog HDL, VHDL Language support:
set_<role name>_oe()
void set_<role name>_oe()
Prototype:
Verilog HDL: enable
VHDL:
enable
Arguments:
void Returns:
Enables the bidirectional ports when the value is set to 1. Description:
Verilog HDL, VHDL Language support:
signal_input_<role name>_change
signal_input_<role name>_change
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Triggers when the input signal for a particular port changes its value. For a
bidirectional port, this event is only triggered if its input value defers from its last
input value. Description:
Verilog HDL Language support:
Conduit BFM Altera Corporation
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