Altera Avalon Verification IP Suite - Manual (Page 17)

Clock_stop()
clock_stop()
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Turns off the clock. Description:
Verilog HDL Language support:
get_run_state()
get_run_state()
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
bit Returns:
Returns the state of the clock source; 1=running, 0=stop. Description:
Verilog HDL Language support:
get_version()
string get_version()
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
string Returns:
Returns BFM version as a string of three integers separated by periods. For example,
version 10.1 sp1 is encoded as "10.1.1". Description:
Verilog HDL Language support:
Clock Source BFM Altera Corporation
Send Feedback
Clock_stop() 2-2