Artesyn SCP-P4040-4G-ENP2 Installation and Use (August 2014) - Manual (Page 31)

Functional Description
SCP-P4040-4G-ENP2 Installation and Use (6806800P60B) 31
4.3 Processor Core and Cache Memory Complex
The QorIQ P4040 has four high-performance 32-bit Power Architecture Book E-compliant
e500mc cores. Each e500mc is a superscalar dual issue processor that supports out-of-order
execution and in-order completion, thus making it perform better than other RISC and CISC
architectures.
Features of e500mc
 36 bit physical addressing
 512-entry 4-Kbyte pages
 3 Integer units (2 simple, 1 complex)
 1.5GHz at 1.0V
 64-Byte cache line size
 L1 caches
 User, Supervisor, and Hypervisor instruction level privileges
 APU, classic double precision floating point unit
 128-Kb private L2 cache running at the same frequency of CPU
 2-Mbyte of shared L3 CoreNet platform cache (CPC)
4.4 Integrated Memory Controller
The P4040 consists of two DDR controllers that support DDR2 and DDR3 SDRAM. It can
support a maximum of 64GByte of main memory. It is capable of ECC, detects and corrects all
single bit errors, double-bit and within a nibble errors. The DDR controller is capable of self-
refresh mode (for compliant DDR SDRAM DIMMs) and an initialization bypass during system
power-on after an abnormal shutdown for use by designers in preventing re-initialization.