Artesyn SCP-P4040-4G-ENP2 Installation and Use (August 2014) - Manual (Page 46)

Functional Description
SCP-P4040-4G-ENP2 Installation and Use (6806800P60B) 46
4.13.2 PHY
dTSEC0@FMan1
is connected to BCM5482 via RGMII. There are totally two ports included in
the GE PHY BCM5482 and only first port is used.The MDIO address for the first port is 0x01 and
the second is 0x02.
The MDIO addresses for 4 SGMII PHYs are 0x1C, 0x1D, 0x1E and 0x1F when SerDes option
#5/#6 or #10 is applied.
4.14 UART Interface
SCP-P4040-4G-ENP2 consists of 4 UARTS (Tx and Rx signals for each UART) or 2 DUARTS (Tx,
Rx, CTS, RTS signals for each DUART) that are routed to the COM Express connectors. Several
optional resistors are provided to determine whether UARTS or DUARTS are routed.
When UARTS are routed, R383, R385, R387, and R389 are installed and R382, R384, R386, and
R388 are removed, and vice versa.
4.15 RTC & WDT
The RTC and WDT functions provided in the module are embedded separated in 2 ICs, U2100
and U2101 respectively. The WDT is accessed through I2C1 bus of the processor, and the RTC
is accessed through I2C2 bus, both with an address of 0xD0.The WDT triggers a reset output
signal for power-on reset, and the RTC provides a 32 KHz clock output for the RTC clock input
of the processor. Battery backup for the RTC is supplied by the VCC_BAT pin on the COME
connectors.
UART option is the default setting.
Table 4-8 Real Time Clock
Characteristic Value
Vendor ST Micro