Epson S1C63000 - Manual (Page 48)

42 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
SUB %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
SUB [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
SUB [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
SBC %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
SBC %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
SBC [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
SBC [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
CMP %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
CMP %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
1 1 0 0 0 0 1 1 1 0 1 0 X
1 1 0 0 0 0 1 1 1 0 1 1 X
1 1 0 0 0 0 1 0 1 i3 i2 i1 i0
1 1 0 0 0 0 1 1 0 0 1 0 0
1 1 0 0 0 0 1 1 0 0 1 0 1
1 1 0 0 0 0 1 1 0 0 1 1 0
1 1 0 0 0 0 1 1 0 0 1 1 1
1 1 0 0 0 0 1 1 0 1 0 0 0
1 1 0 0 0 0 1 1 0 1 1 0 0
1 1 0 0 0 0 0 0 0 i3 i2 i1 i0
1 1 0 0 0 0 1 1 0 1 0 0 1
1 1 0 0 0 0 1 1 0 1 1 0 1
1 1 0 0 0 0 0 0 1 i3 i2 i1 i0
1 1 0 0 0 0 1 1 0 1 0 1 0
1 1 0 0 0 0 1 1 0 1 1 1 0
1 1 0 0 0 0 0 1 0 i3 i2 i1 i0
1 1 0 0 0 0 1 1 0 1 0 1 1
1 1 0 0 0 0 1 1 0 1 1 1 1
1 1 0 0 0 0 0 1 1 i3 i2 i1 i0
1 1 0 0 0 1 1 1 1 0 0 0 X
1 1 0 0 0 1 1 1 1 0 0 1 X
1 1 0 0 0 1 1 0 0 i3 i2 i1 i0
1 1 0 0 0 1 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 0 0 0 0 1
1 1 0 0 0 1 1 1 0 0 0 1 0
1 1 0 0 0 1 1 1 0 0 0 1 1
1 1 0 0 0 1 1 1 1 0 1 0 X
1 1 0 0 0 1 1 1 1 0 1 1 X
1 1 0 0 0 1 1 0 1 i3 i2 i1 i0
1 1 0 0 0 1 1 1 0 0 1 0 0
1 1 0 0 0 1 1 1 0 0 1 0 1
1 1 0 0 0 1 1 1 0 0 1 1 0
1 1 0 0 0 1 1 1 0 0 1 1 1
1 1 0 0 0 1 1 1 0 1 0 0 0
1 1 0 0 0 1 1 1 0 1 1 0 0
1 1 0 0 0 1 0 0 0 i3 i2 i1 i0
1 1 0 0 0 1 1 1 0 1 0 0 1
1 1 0 0 0 1 1 1 0 1 1 0 1
1 1 0 0 0 1 0 0 1 i3 i2 i1 i0
1 1 0 0 0 1 1 1 0 1 0 1 0
1 1 0 0 0 1 1 1 0 1 1 1 0
1 1 0 0 0 1 0 1 0 i3 i2 i1 i0
1 1 0 0 0 1 1 1 0 1 0 1 1
1 1 0 0 0 1 1 1 0 1 1 1 1
1 1 0 0 0 1 0 1 1 i3 i2 i1 i0
1 1 1 1 0 0 1 1 1 X 0 0 0
1 1 1 1 0 0 1 1 1 X 0 1 0
1 1 1 1 0 0 1 0 0 i3 i2 i1 i0
1 1 1 1 0 0 1 1 0 0 0 0 0
1 1 1 1 0 0 1 1 0 0 0 0 1
1 1 1 1 0 0 1 1 0 0 0 1 0
1 1 1 1 0 0 1 1 0 0 0 1 1
1 1 1 1 0 0 1 1 1 X 1 0 0
1 1 1 1 0 0 1 1 1 X 1 1 0
1 1 1 1 0 0 1 0 1 i3 i2 i1 i0
1 1 1 1 0 0 1 1 0 0 1 0 0
1 1 1 1 0 0 1 1 0 0 1 0 1
1 1 1 1 0 0 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1 0 0 1 1 1
1 ↓ – Ч
1
↓
–
↓ ↑ Ч
1 ↓ – Ч
1
↓
– ●
1 ↓ – Ч
1
↓
– ●
1 ↓ – Ч
2
↓
– ●
2 ↓ – ●
2
↓
– ●
2 ↓ – Ч
2
↓
–
Ч
2 ↓ – Ч
2
↓
– ●
2 ↓ – ●
2
↓
– ●
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
2
↓
– ●
2
↓
– ●
2 ↓ – ●
2
↓
–
Ч
2 ↓ – Ч
2
↓
–
Ч
2 ↓ – ●
2
↓
– ●
2 ↓ – ●
2
↓
–
Ч
2 ↓ – Ч
2
↓
–
Ч
1 ↓ – ↓ ↑ Ч
1
↓
–
Ч
1 ↓ – Ч
1
↓
– ●
1 ↓ – Ч
1
↓
– ●
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
↓ ↑ Ч
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
B ← B-A
B
←
B-B
B ← B-imm4
B
←
B-[X]
B ← B-[X], X ← X+1
B
←
B-[Y]
B ← B-[Y], Y ← Y+1
[X]
←
[X]-A
[X] ← [X]-B
[X]
←
[X]-imm4
[X] ← [X]-A, X ← X+1
[X]
←
[X]-B, X
←
X+1
[X] ← [X]-imm4, X ← X+1
[Y]
←
[Y]-A
[Y] ← [Y]-B
[Y]
←
[Y]-imm4
[Y]
←
[Y]-A, Y
←
Y+1
[Y]
←
[Y]-B, Y
←
Y+1
[Y]
←
[Y]-imm4, Y
←
Y+1
A
←
A-A-C
A
←
A-B-C
A
←
A-imm4-C
A
←
A-[X]-C
A
←
A-[X]-C, X
←
X+1
A
←
A-[Y]-C
A
←
A-[Y]-C, Y
←
Y+1
B
←
B-A-C
B
←
B-B-C
B
←
B-imm4-C
B
←
B-[X]-C
B
←
B-[X]-C, X
←
X+1
B
←
B-[Y]-C
B
←
B-[Y]-C, Y
←
Y+1
[X]
←
[X]-A-C
[X]
←
[X]-B-C
[X] ← [X]-imm4-C
[X]
←
[X]-A-C, X
←
X+1
[X] ← [X]-B-C, X ← X+1
[X]
←
[X]-imm4-C, X
←
X+1
[Y] ← [Y]-A-C
[Y]
←
[Y]-B-C
[Y] ← [Y]-imm4-C
[Y]
←
[Y]-A-C, Y
←
Y+1
[Y] ← [Y]-B-C, Y ← Y+1
[Y]
←
[Y]-imm4-C, Y
←
Y+1
A-A
A-B
A-imm4
A-[X]
A-[X], X ← X+1
A-[Y]
A-[Y], Y
←
Y+1
B-A
B-B
B-imm4
B-[X]
B-[X], X
←
X+1
B-[Y]
B-[Y], Y
←
Y+1
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode 12 E I C Z 11 10 9 8 7 6 5 4 3 2 1 0
↔ ↔
ALU alithmetic operation (2/3)
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135
135
135
136
136
136
136
137
137
138
137
137
138
137
137
138
137
137
138
123
123
124
124
125
124
125
123
123
124
124
125
124
125
125
125
126
126
126
127
125
125
126
126
126
127
84
84
84
85
85
85
85
84
84
84
85
85
85
85