And %r,imm4, And %f,imm4 – Epson S1C63000 User Manual
Page 80
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EPSON
S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
AND %r,imm4
Logical AND of immediate data imm4 and r reg.
1 cycle
Function:
r
←
r
∧
imm4
Performs a logical AND operation of the 4-bit immediate data imm4 and the content of the r
register (A or B), and stores the result in the r register.
Code:
Mnemonic
MSB
LSB
AND %A,imm4
1
1
0
1
0
0
1
0
0 i3 i2 i1 i0
1A40H–1A4FH
AND %B,imm4
1
1
0
1
0
0
1
0
1 i3 i2 i1 i0
1A50H–1A5FH
Flags:
E
I
C
Z
↓
–
–
↕
Mode:
Src: Immediate data
Dst: Register direct
Extended addressing: Invalid
AND %F,imm4
Logical AND of immediate data imm4 and F reg.
1 cycle
Function:
F
←
F
∧
imm4
Performs a logical AND operation of the 4-bit immediate data imm4 and the content of the F
(flag) register, and stores the result in the r register. It is possible to reset any flag.
Code:
Mnemonic
MSB
LSB
AND %F,imm4
1
0
0
0
0
1
0
0
0 i3 i2 i1 i0
1080H–108FH
Flags:
E
I
C
Z
↓
↓
↓
↓
Mode:
Src: Immediate data
Dst: Register direct
Extended addressing: Invalid