Bit %r,[%ir] bit %r,[%ir – Epson S1C63000 User Manual
Page 85
S1C63000 CORE CPU MANUAL
EPSON
79
CHAPTER 4: INSTRUCTION SET
BIT %r,[%ir]
BIT %r,[%ir]+
Test bit of r reg. with location [ir reg.] and increment ir reg.
1 cycle
Function:
r
∧
[ir], ir
←
ir + 1
Performs a logical AND of the content of the data memory addressed by the ir register (X or Y)
and the content of the r register (A or B) to check the bits of the r register. The Z flag is changed
due to the operation result, but the content of the register is not changed. Then increments the
ir register (X or Y). The increment result of the ir register does not affect the flags.
Code:
Mnemonic
MSB
LSB
BIT %A,[%X]+
1
1
0
1
0
1
1
1
0
0
0
0
1
1AE1H
BIT %A,[%Y]+
1
1
0
1
0
1
1
1
0
0
0
1
1
1AE3H
BIT %B,[%X]+
1
1
0
1
0
1
1
1
0
0
1
0
1
1AE5H
BIT %B,[%Y]+
1
1
0
1
0
1
1
1
0
0
1
1
1
1AE7H
Flags:
E
I
C
Z
↓
–
–
↕
Mode:
Src: Register indirect
Dst: Register direct
Extended addressing: Invalid
Test bit of r reg. with location [ir reg.]
1 cycle
Function:
r
∧
[ir]
Performs a logical AND of the content of the data memory addressed by the ir register (X or Y)
and the content of the r register (A or B) to check the bits of the r register. The Z flag is changed
due to the operation result, but the content of the register is not changed.
Code:
Mnemonic
MSB
LSB
BIT %A,[%X]
1
1
0
1
0
1
1
1
0
0
0
0
0
1AE0H
BIT %A,[%Y]
1
1
0
1
0
1
1
1
0
0
0
1
0
1AE2H
BIT %B,[%X]
1
1
0
1
0
1
1
1
0
0
1
0
0
1AE4H
BIT %B,[%Y]
1
1
0
1
0
1
1
1
0
0
1
1
0
1AE6H
Flags:
E
I
C
Z
↓
–
–
↕
Mode:
Src: Register indirect
Dst: Register direct
Extended addressing: Valid
Extended
LDB
%EXT,imm8
operation:
BIT
%r,[%X]
r
∧
[00imm8] (00imm8 = 0000H + 00H to FFH)
LDB
%EXT,imm8
BIT
%r,[%Y]
r
∧
[FFimm8] (FFimm8 = FF00H + 00H to FFH)