Alu logic operation (1/2) – Epson S1C63000 User Manual
Page 50
44
EPSON
S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
AND
%A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
AND
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
AND
%F,imm4
AND
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
AND
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
OR
%A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
OR
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
OR
%F,imm4
OR
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
OR
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
1 1 0 1 0 0 1 1 1 0 0 0 X
1 1 0 1 0 0 1 1 1 0 0 1 X
1 1 0 1 0 0 1 0 0 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 0 0 0 0
1 1 0 1 0 0 1 1 0 0 0 0 1
1 1 0 1 0 0 1 1 0 0 0 1 0
1 1 0 1 0 0 1 1 0 0 0 1 1
1 1 0 1 0 0 1 1 1 0 1 0 X
1 1 0 1 0 0 1 1 1 0 1 1 X
1 1 0 1 0 0 1 0 1 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 0 1 0 1
1 1 0 1 0 0 1 1 0 0 1 1 0
1 1 0 1 0 0 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 1 0 0 0
1 1 0 1 0 0 1 1 0 1 1 0 0
1 1 0 1 0 0 0 0 0 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 1 0 0 1
1 1 0 1 0 0 1 1 0 1 1 0 1
1 1 0 1 0 0 0 0 1 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 1 0 1 0
1 1 0 1 0 0 1 1 0 1 1 1 0
1 1 0 1 0 0 0 1 0 i3 i2 i1 i0
1 1 0 1 0 0 1 1 0 1 0 1 1
1 1 0 1 0 0 1 1 0 1 1 1 1
1 1 0 1 0 0 0 1 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 1 0 0 0 X
1 1 0 1 1 0 1 1 1 0 0 1 X
1 1 0 1 1 0 1 0 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 0 0 0 0
1 1 0 1 1 0 1 1 0 0 0 0 1
1 1 0 1 1 0 1 1 0 0 0 1 0
1 1 0 1 1 0 1 1 0 0 0 1 1
1 1 0 1 1 0 1 1 1 0 1 0 X
1 1 0 1 1 0 1 1 1 0 1 1 X
1 1 0 1 1 0 1 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 0 1 0 0
1 1 0 1 1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0 0 1 1 0
1 1 0 1 1 0 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 0 0
1 1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 1 1 0 0 0 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 0 1
1 1 0 1 1 0 1 1 0 1 1 0 1
1 1 0 1 1 0 0 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 1 0
1 1 0 1 1 0 1 1 0 1 1 1 0
1 1 0 1 1 0 0 1 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 1 1
1 1 0 1 1 0 1 1 0 1 1 1 1
1 1 0 1 1 0 0 1 1 i3 i2 i1 i0
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓ ↓ ↓ ↓
Ч
2
↓
– –
●
2
↓
– –
●
2
↓
– –
●
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
●
2
↓
– –
●
2
↓
– –
●
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↓
– –
●
1
↓
– –
Ч
1
↑ ↑ ↑ ↑
Ч
2
↓
– –
●
2
↓
– –
●
2
↓
– –
●
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
●
2
↓
– –
●
2
↓
– –
●
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
Ч
A
←
A
∧
A
A
←
A
∧
B
A
←
A
∧
imm4
A
←
A
∧
[X]
A
←
A
∧
[X], X
←
X+1
A
←
A
∧
[Y]
A
←
A
∧
[Y], Y
←
Y+1
B
←
B
∧
A
B
←
B
∧
B
B
←
B
∧
imm4
B
←
B
∧
[X]
B
←
B
∧
[X], X
←
X+1
B
←
B
∧
[Y]
B
←
B
∧
[Y], Y
←
Y+1
F
←
F
∧
imm4
[X]
←
[X]
∧
A
[X]
←
[X]
∧
B
[X]
←
[X]
∧
imm4
[X]
←
[X]
∧
A, X
←
X+1
[X]
←
[X]
∧
B, X
←
X+1
[X]
←
[X]
∧
imm4, X
←
X+1
[Y]
←
[Y]
∧
A
[Y]
←
[Y]
∧
B
[Y]
←
[Y]
∧
imm4
[Y]
←
[Y]
∧
A, Y
←
Y+1
[Y]
←
[Y]
∧
B, Y
←
Y+1
[Y]
←
[Y]
∧
imm4, Y
←
Y+1
A
←
A
∨
A
A
←
A
∨
B
A
←
A
∨
imm4
A
←
A
∨
[X]
A
←
A
∨
[X], X
←
X+1
A
←
A
∨
[Y]
A
←
A
∨
[Y], Y
←
Y+1
B
←
B
∨
A
B
←
B
∨
B
B
←
B
∨
imm4
B
←
B
∨
[X]
B
←
B
∨
[X], X
←
X+1
B
←
B
∨
[Y]
B
←
B
∨
[Y], Y
←
Y+1
F
←
F
∨
imm4
[X]
←
[X]
∨
A
[X]
←
[X]
∨
B
[X]
←
[X]
∨
imm4
[X]
←
[X]
∨
A, X
←
X+1
[X]
←
[X]
∨
B, X
←
X+1
[X]
←
[X]
∨
imm4, X
←
X+1
[Y]
←
[Y]
∨
A
[Y]
←
[Y]
∨
B
[Y]
←
[Y]
∨
imm4
[Y]
←
[Y]
∨
A, Y
←
Y+1
[Y]
←
[Y]
∨
B, Y
←
Y+1
[Y]
←
[Y]
∨
imm4, Y
←
Y+1
Mnemonic
Machine code
Operation
Cycle
Page
Flag
EXT.
mode
12
E I C Z
11 10 9 8 7 6 5 4 3 2 1 0
↔
ALU logic operation (1/2)
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73
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