Appendices, 4) other devices, Table 4.8 other devices list – MITSUBISHI ELECTRIC MOTION CONTROLLERS Q172DCPU User Manual

Page 168

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APP - 33

APPENDICES

(4) Other devices

Table 4.8 Other devices list

Item Q173DCPU/Q172DCPU

Q173HCPU/Q172HCPU

M2320 to M2399

Unusable

Special relay allocated devices (Status)

M2400 to M3039

Device area of 9 axes or more is usable as user
devices in Q172DCPU.

Device area of 9 axes or more is unusable as
user devices in Q172HCPU.

M3136 to M3199

Unusable

Special relay allocated devices
(Command signal)

M3200 to M3839
D0 to D639

Internal relays/
Data registers

D640 to D703

Device area of 9 axes or more is usable as user
devices in Q172DCPU.

Device area of 9 axes or more is unusable in
Q172HCPU.

Personal computer link
communication error flag

— M2034

PCPU READY complete

SM500

D759

D9 + 20n (Data shortened to 1 word)

(Note-1)

Home position return re-travel value

#8006 + 20n, #8007 + 20n

(Referring at monitoring)

(Note-1)

D9 + 20n

(Note-1)

Travel value change registers

Optional device

(Set for D16 + 20n, D17 + 20n are also usable.)

(Note-1)

D16 + 20n, D17 + 20n

(Note-1)

D0 to D8191

D800 to D8191

W0 to W1FFF

W0 to W1FFF

#0 to #7999

#0 to #7999

Indirect setting devices
(Word devices)

U \G10000 to U \G(10000 + p – 1)

(Note-2)

X0 to X1FFF

X0 to X1FFFF

Y0 to Y1FFF

Y0 to Y1FFF

M0 to M8191

M/L0 to M/L8191

M9000 to M9255

B0 to B1FFF

B0 to B1FFF

F0 to F2047

F0 to F2047

Indirect setting devices
(Bit devices)

U \G10000.0 to U \G(10000 + p – 1).F

(Note-2)

D0 to D8191

D800 to D3069, D3080 to D8191

W0 to W1FFF

W0 to W1FFF

High-speed reading function
settable devices

U \G10000 to U \G(10000 + p – 1)

(Note-2)

D0 to D8191

D0 to D8191

W0 to W1FFF

W0 to W1FFF

#0 to #7999

#0 to #7999

Optional data monitor function
settable devices

U \G10000 to U \G(10000 + p – 1)

(Note-2)

(Note-1) : "n" in the above device No. indicates the numerical value which correspond to axis No.
(Note-2) : "p" indicates the user setting area points of Multiple CPU high speed transmission area in each CPU.

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