2 multiple cpu system, 2) system configuration, B) example of using automatic refresh method – MITSUBISHI ELECTRIC MOTION CONTROLLERS Q172DCPU User Manual

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2 MULTIPLE CPU SYSTEM

(b) Example of using automatic refresh method

INC

SM400

SM400

PLC program

CPU No.1 (PLC CPU)

CPU shared memory

(Automatic refresh area

(Note-1)

)

D0

Y0

INC D1

Y0

END

D0

1)

2)

3)

CPU No.2 (Motion CPU)

CPU No.1

transmitting

data

D2000

Device memory

CPU shared memory

(Automatic refresh area

(Note-1)

)

Parameter

Device memory

Refresh at the
timing of END
processing

Refresh at the
timing of Motion
CPU main cycle

CPU No.1 to CPU No.2

Transmit D0

CPU No.1 to CPU No.2

Receive D2000

CPU No.1

transmitting

data

Multiple CPU high speed
transmission in 0.88ms cycle

Parameter

1) Transmit the content of D0 to the automatic refresh area

(Note-1)

at the time of END processing by parameter setting.

2) Transmit the content of automatic refresh area

(Note-1)

to the other CPU by Multiple CPU high speed transmission at 0.88ms cycle.

3) Read the content of automatic refresh area

(Note-1)

at the time of Motion CPU main cycle and transmit it to D2000 by parameter setting.

. Note-1: The area composed in the Multiple CPU high speed transmission area.

(Refer to Section "(3) Memory configuration of Multiple CPU high speed transmission area".)

(2) System configuration

Multiple CPU high speed transmission can be used only between CPU modules
for the Multiple CPU high speed transmission installed in the Multiple CPU high
speed main base unit (Q3 DB).
The system configuration specification is shown in Table 2.4.

Table 2.4 System configuration to use Multiple CPU high speed

transmission

Object Restrictions

Base unit

Multiple CPU high speed main base unit (Q3 DB) is used.
QnUD(H)CPU is used for CPU No. 1.

CPU module

Q173DCPU/Q172DCPU and QnUD(H)CPU are used for CPU No. 2 to
CPU No. 4


"MULTI EXE. ERROR (error code: 7011) will occur if the power supply of Multiple
CPU system is turned on without matching the system configuration shown in
Table 2.4.

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