Motorola SSETM 5000 - Manual (Page 42)

November 11, 2004 6881094C12-A
2-20 Theory of Operation: VOCON Board
Microcontroller Unit (MCU)
The MCU portion of the dual-core processor controls receive/transmit frequencies, power levels,
display, and other radio functions, using either direct logic control or serial communications paths to
the devices. The microcontrol unit executes a stored program located in the FLASH memory device.
Data is transferred to and from memory by the microcontrol unit data bus. The memory location from
which data is read, or to which data is written, is selected by the address lines. The microcontrol unit
requires a 16.8 MHz clock and a 32.768 kHz clock.
The MCU portion of the dual-core processor has 22.5k x 32 bits of internal RAM and 1k x 32 bits of
internal ROM, which is used for the bootstrapping code. The MCU has several peripherals including
an External Interface Module (EIM), the Multiple Queue Serial Peripheral Interface (MQSPI), two
Universal Asynchronous Receiver/Transmitter (UART) modules, and the One-Wire Interface
module. The MCU communicates internally to the DSP through the MCU/DSP Interface (MDI).
External Interface Module (EIM)
The External Interface Module (EIM) is the MCU interface to the SRAM U403 and Flash Memory
U402. The EIM lines include 24 external address lines, 16 external bi-directional data lines, 6 chip
selects lines, read/write line, and output enable line among others. All of the EIM lines operate at 1.8-
V logic levels, and the EIM operates at the MCU clock speed.
Multiple Queue Serial Peripheral Interface (MQSPI)
The Multiple Queue Serial Peripheral Interface (MQSPI) is the MCUs programming interface to other
ICs. The dual-core processor has two independent SPI busses, and each has its own clock line (test
points SCKA and SCKB), data-out line (test points MOSIA and MOSIB), and data-in line (test points
MISOA and MISOB). There are 10 SPI chip selects (SPICS) that are programmable to either SPI A,
the transceiver board SPI bus, or to SPI B, the dedicated VOCON SPI bus.
The devices on the SPI A bus include the PCIC and FracN IC on the SPICS4 (R131), the Abacus III
IC on SPICS5 (R126), an analog-to-digital converter (ADC) on SPICS6 (R133), and the serial
EEPROM on SPICS7 (R132). The two SPI B chip selects are for the GCAP II IC U501 on SPICS2
(R539) and the digital-support IC U301 on SPICS3. All of the SPI module lines operate at GPIO
voltage logic levels.
There are several devices on the transceiver board that only have one bi-directional SPI data line.
Components U404, U405, and U406 are configurable by MCU GPIO pin TOUT13 (MISOA_SEL) to
route the data line to the appropriate pin on the dual-core processor depending on which SPI device
is being accessed.
Universal Asynchronous Receiver/Transmitter (UART)
The dual-core processor has two Universal Asynchronous Receiver/Transmitter (UART) modules.
UART1 handles the RS232 lines while UART 2 is connected to the SB9600 lines. Each UART has a
receive data line (URXD), a transmit data line (UTXD), and hardware flow control signals (RTS–
request to send) and (CTS–clear to send). All UART lines operate at GPIO voltage logic levels. The
translation to 5 V logic levels for the accessory side connector is discussed in
Section 2.5.2.3.1:
“Digital-Support IC U301” on page 2-26 .
One-Wire Interface
The MCU has a One-Wire Interface module that is used to communicate to a One-Wire device like a
USB cable or a smart battery using the Dallas Semiconductor protocol. This module uses a GPIO
voltage logic level.