Motorola SSETM 5000 - Manual (Page 50)

November 11, 2004 6881094C12-A
2-28 Theory of Operation: VOCON Board
Watchdog Timer
The digital-support IC monitors the position of the radio’s On/Off switch on the BP_SEN_X pin, and
that signal is located on Q508 pin 3. If the voltage on pin 3 is ground, then the radio is turned on. If
the voltage on pin 3 is 3 volts, then the radio is off. When the radio is turned off, a counter inside the
digital-support IC begins incrementing. That counter can be refreshed by the dual-core processor
through the SPI bus.
This is done so that the software has enough time to complete its tasks before the power is taken
away from the dual-core processor. If the counter is not refreshed by the time the count is complete,
the digital-support IC pin WD_OUT goes low, which shuts down the GCAP II voltage regulators.
During normal radio operation, WD_OUT should be high (V2 regulated voltage).
32 kHz Oscillator and CMOS Output
The 32 kHz oscillator circuitry uses a separate voltage supply pin (VDD3_XTL) than the other 3-V
portions of the digital-support IC. The oscillator circuitry is internal to the digital-support IC, and the
32.768 kHz crystal Y301 and additional load capacitors C308 and C309 are located next to the IC.
The output of the 32 kHz oscillator is an LI_CELL voltage (approximately 3 volts peak-to-peak),
32.768 kHz square wave on pin REF32_OUT. This clock goes to two destinations: the dual-core
processor CKIL pin (32 kHz test point) as a square wave and the GCAP II IC XTAL1 pin (C306) as a
sine wave.
Components C306 and C313 are used to filter the square wave into a sine wave before the signal
goes to the GCAP II IC.
13 MHz Reference Generation for GCAP II IC
The 13 MHz reference is required by the GCAP II IC for the CODEC time base and the SSI clock
generator module internal to the digital-support IC. A phase locked loop (PLL) is used to generate
the 13 MHz using the 16.8 MHz clock, which is provided to the digital-support IC REF_16_IN pin
(C307). An external RC loop filter network, consisting of R301, C301, and C302, is connected to the
PLL_LFT pin.
The 13 MHz reference output pin, REF_13_OUT, is conditioned by the RC network of R302 and
C303. The signal at REF_13_OUT is a 3-V peak-to-peak square wave, and the RC filter produces a
lower-level triangle wave that is suitable for the GCAP II IC.
The 13 MHz reference is disabled as the digital-support IC powers up. The 13 MHz reference is
enabled by the dual-core processor through the SPI bus, and, during normal radio operation, this
signal should be present.