Samsung S3C2440A - Manual (Page 198)

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER
6-13
CONTROL REGISTER
Register Address R/W Description Reset Value
NFCONT 0x4E000004 R/W NAND Flash control register 0x0384
NFCONT Bit Description Initial State
Reserved [14:15] Reserved 0
Lock-tight [13] Lock-tight configuration
0: Disable lock-tight 1: Enable lock-tight,
Once this bit is set to 1, you cannot clear. Only reset or
wake up from sleep mode can make this bit disable(can
not cleared by software).
When it is set to 1, the area setting in
NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1 is
unlocked, and except this area, write or erase command
will be invalid and only read command is valid.
When you try to write or erase locked area, the illegal
access will be occur (NFSTAT[3] bit will be set).
If the NFSBLK and NFEBLK are same, entire area will be
locked.
0
Soft Lock [12] Soft Lock configuration
0: Disable lock 1: Enable lock
Soft lock area can be modified at any time by software.
When it is set to 1, the area setting in
NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1 is
unlocked, and except this area, write or erase command
will be invalid and only read command is valid.
When you try to write or erase locked area, the illegal
access will be occur (NFSTAT[3] bit will be set).
If the NFSBLK and NFEBLK are same, entire area will be
locked.
1
Reserved [11] Reserved 0
EnbIllegalAccINT [10] Illegal access interrupt control
0: Disable interrupt 1: Enable interrupt
Illegal access interrupt is occurred when CPU tries to
program or erase locking area (the area setting in
NFSBLK(0x4E000038) to NFEBLK(0x4E00003C)-1).
0
EnbRnBINT [9] RnB status input signal transition interrupt control
0: Disable RnB interrupt 1: Enable RnB interrupt
0
RnB_TransMode [8] RnB transition detection configuration
0: Detect rising edge 1: Detect falling edge
0
Reserved [7] Reserved 0
SpareECCLock [6] Lock Spare area ECC generation. 1