Samsung S3C2440A - Manual (Page 547)

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA
27-29
SCLK
nSRAS
tSAD
Trp
nSCAS
DATA
ADDR/BA
nBEx
tSRD
SCKE
A10/AP
nGCSx
tSCSD
nWE
tSAD
tSCD
tSWD
tSAD
tSCSD
tSRD
'1'
'1'
'HZ'
Trc
tCKED
'HZ'
'1'
'1'
'1'
'1'
'1'
tCKED
NOTE: Before executing an auto/self refresh command, all the banks must be in idle state.
Figure 27-27 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4)