Samsung S3C2440A - Manual (Page 199)

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR
6-14
0: Unlock Spare ECC 1: Lock Spare ECC
Spare area ECC status register is
NFSECC(0x4E000034),
MainECCLock [5] Lock Main data area ECC generation
0: Unlock Main data area ECC generation
1: Lock Main data area ECC generation
Main area ECC status register is
NFMECC0/1(0x4E00002C/30),
1
InitECC [4] Initialize ECC decoder/encoder(Write-only)
1: Initialize ECC decoder/encoder
0
Reserved [2:3] Reserved 00
Reg_nCE [1] NAND Flash Memory nFCE signal control
0: Force nFCE to low(Enable chip select)
1: Force nFCE to High(Disable chip select)
Note: During boot time, it is controlled automatically.
This value is only valid while MODE bit is 1
1
MODE [0] NAND Flash controller operating mode
0: NAND Flash Controller Disable (Don’t work)
1: NAND Flash Controller Enable
0