Samsung S3C2440A User Manual
Page 203
NAND FLASH CONTROLLER
S3C2440A RISC MICROPROCESSOR
6-18
NFCON STATUS REGISTER
Register
Address
R/W
Description
Reset Value
NFSTAT
0x4E000020 R/W NAND Flash operation status register
0xXX00
NFSTAT Bit
Description
Initial
State
Reserved [7]
Reserved
X
Reserved [4:6]
Reserved
0
IllegalAccess [3]
Once Soft Lock or Lock-tight is enabled, The illegal access
(program, erase) to the memory makes this bit set.
0: illegal access is not detected
1: illegal access is detected
0
RnB_TransDetect [2] When RnB low to high transition is occurred, this value set and
issue interrupt if enabled. To clear this value write ‘1’.
0: RnB transition is not detected
1: RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
0
nCE
(Read-only)
[1]
The status of nCE output pin
1
RnB
(Read-only)
[0]
The status of RnB input pin.
0: NAND Flash memory busy
1: NAND Flash memory ready to operate
1