Fig.7-7: status and error registers diagram, Status registers, Fault registers – TDK GENESYS 1500W User Manual

Page 71: Serial txd

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83-507-013 Rev. D

63

SRQ

Messages

Response

messages

Command Error (”Cnn”)

Execution Error (”Enn”)

Query Response (”message”)

Command Response (”OK”)

CV
CC

NFLT

FLT

AST
FDE

0

LCL

CV
CC

NFLT

FLT

0
0
0

LCL

0
0
0

Status Registers

Condition

Enable

Event

Constant Voltage
Constant Current
No Fault
Fault
Auto Start
Fold Enabled

Spare

Local Mode

0
1

2

3

4

5
6

7

“STAT?” “SENA xx”

“SENA?”

“SEVE?”

0

AC

OTP
FLD
OVP

SO

OFF

ENA

Fault Registers

Condition

Enable

Spare
AC Fail
Over Temperature
Foldback (tripped)
Over Volt Prot

Shut Off (rear panel)

Output Off (front panel)

Enable Open

0
1

2

3

4

5
6

7

“FLT?”

“FENA xx”
“FENA?”

0

AC

OTP

FLD

OVP

SO

OFF

ENA

Event

“FEVE?”

MSB

MSB

LSB

Serial

TXD

LSB

One response for every command

or query received.

One SRQ when SEVE goes
from all zeroes to any bit set.
Setting more SEVE bits does
not cause more SRQs.

Positive Logic:
0 = No Event
1 = Event Occured

Fig.7-7: Status and Error Registers Diagram

“Inn” and CR

7.11.2 Conditional Registers
The fault Condition Register and the Status Condition Register are read only registers that the user
may read to see the condition of the Power supply. Refer to Table 7-8 for description of the Fault
Condition Register bits and Table 7-9 for the Status Condition register bits.

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