Document Outline

• Features
• Description
• Block Diagram
• Pin Description
  • Signals
  • Port Structure Description
    • Quasi Bi-directional Output Configuration
    • Push-pull Output Configuration
    • LED Output Configuration
• SFR Mapping
• PowerMonitor
  • Description
  • PowerMonitor Diagram
• Power Monitoring and Clock Management
  • Idle Mode
  • Power-down Mode
    • Entering Power-down Mode
    • Exit from Power-down Mode
    • SCI Control
    • LED Control
    • Low Power Mode
    • Reduced EMI Mode
    • Power Modes Control Registers
• Clock Management
  • Functional Block Diagram
  • X2 Feature
    • Description
  • Clock Prescaler
  • Clock Control Registers
    • Clock Prescaler Register
• DC/DC Clock
  • Clock Control Register
  • Clock Prescaler
• Smart Card Interface Block (SCIB)
  • Introduction
  • Main Features
  • Block Diagram
  • Functional Description
    • Barrel Shifter
    • SCART FSM
    • ETU Counter
    • Guard Time Counter
    • Waiting Time Counter (WT)
    • Power-on and Power-off FSM
    • Interrupt Generator
    • Registers
  • Other Features
    • Clock
    • Alternate Card
    • Card Presence Input
    • SCIB Reset
  • DC/DC Converter
  • Registers Description
• Interrupt System
  • INT1 Interrupt Vector
    • INT1/OE Input
    • Rxd Input
    • CPRES Input
• LED Ports Configuration
  • Registers Definition
• Dual Data Pointer
• Memory Management
  • Program Memory
    • ROM Configuration Byte
    • Program ROM Lock Bits
    • Memory Mapping
    • T89C5121 Flash ROM Version
    • T85C121 Code RAM Version
    • T83C5121 with Mask ROM Version
  • In-System Programming
    • Hardware Interface
    • EEPROM Mapping
    • Bootloader Functional Diagram
    • In-System Programming Timings
  • Protection Mechanisms
    • Transfer Checks
    • Read/Write Protection
      • Lock Byte
      • Configuration Bits
    • UART Protocol
      • Overview
      • Physical Layer
      • Datas and Limits
      • Frame Description
      • Command Description
  • Autobaud
  • Protection Mechanisms
    • Transfer Checks
    • Security
• Timers/Counters
  • Introduction
  • Timer 0/Counter Operations
  • Timer 0
    • Mode 0 (13-bit Timer 0)
    • Mode 1 (16-bit Timer 0)
    • Mode 2 (8-bit Timer 0 with Auto-Reload)
    • Mode 3 (Two 8-bit Timer 0s)
  • Timer 1
    • Mode 0 (13-bit Timer 0)
    • Mode 1 (16-bit Timer 0)
    • Mode 2 (8-bit Timer 0 with Auto-Reload)
    • Mode 3 (Halt)
  • Registers
• Serial I/O Port
  • Framing Error Detection
  • Automatic Address Recognition
    • Given Address
    • Broadcast Address
    • Reset Addresses
  • UART Output Configuration
    • Voltage Level
    • Output Enable Function
  • UART Control Registers
• UART Timings
  • Mode Selection
  • Baud Rate Generator
    • Timer 1
    • Internal Baud Rate Generator
    • Synchronous Mode (Mode 0)
    • Transmission (Mode 0)
    • Reception (Mode 0)
    • Baud Rate Selection (Mode 0)
  • Asynchronous Modes (Modes 1, 2 and 3)
    • Mode 1
    • Modes 2 and 3
    • Transmission (Modes 1, 2 and 3)
    • Reception (Modes 1, 2 and 3)
    • Framing Error Detection (Modes 1, 2 and 3)
    • Baud Rate Selection (Modes 1 and 3)
    • Baud Rate Selection (Mode 2)
• Hardware Watchdog Timer
  • Using the WDT
  • WDT during Power-down and Idle
• Electrical Characteristics
  • Absolute Maximum Ratings
  • DC Parameters
• Typical Application
• Ordering Information
• Package Drawings
  • SSOP24
  • PLCC52
  • QFN32
• Document Revision History for T8xC5121
  • Changes from 4164B - 06/02 to 4164C - 07/03
  • Changes from 4164C - 07/03 to 4164D - 12/03
  • Changes from 4164D - 12/03 to 4164E - 01/04
  • Changes from 4164E - 01/04 to 4164F 11/05
  • Changes from 4164F 11/05 to 4164F 07/06
• Table of Contents