Maxim Integrated Secure Microcontroller - Manual (Page 121)

Secure Microcontroller User’s Guide
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sample times by the bit detector, is the one shifted into the receive shift register. Just after the logic level
is detected during the 10th bit time, the control logic tests to see if the following conditions are true:
a) The previous state of RI was 0.
b) SM2 = 0; or if SM2 = 1, then if the 10th received bit = 1.
During data transmission, the clocking frequency provided by the output of Timer 1 is divided down by a
If both of these conditions are met during the 10th bit time, then the control logic will not perform another
shift, but will instead load the contents of the Receive Shift register into the Receive Data Buffer, load the
logic state determined at the Stop bit time into the RB8 status flag (if SM2=0), and set the RI bit. A serial
interrupt will then be generated if it the appropriate enable bits have been set. If the above conditions are
not satisfied during the stop bit time, then the received word is lost.
The first condition is interpreted by the control logic to mean an “overrun” condition has been detected.
This means that a serial data word has been received before software read the previous word from the
Receive Data Buffer. Only a hardware reset or writing logic 0 to the RI bit will clear RI. It is therefore
recommended that software clear the RI bit after reading from the SBUF register. This signals the
hardware that a properly received data word has been processed by the application software. In an
overrun condition with RI = 1, the originally received word remains in the receive data buffer and all
successively received data words are lost. When SM2 = 1, received data words are selectively discarded
in a manner depending on the asynchronous mode selected. The operational details that are unique to
each of the asynchronous modes are summarized below.
Mode 1
In Mode 1, the asynchronous serial data word is ten bits long, including one start bit, eight data bits, and
one stop bit. The baud rate generation is derived from the Timer 1 overflow output and is therefore
programmable.
Figure 14-2 is a functional block diagram of the operation of the serial I/O port in Mode 1
operation including the timing waveform.
In Mode 1 operation, the SM2 bit may be used to discard a received serial data word in which a “framing
error” is detected, i.e., when a valid stop bit has not been detected. When SM2 = 1, the incoming serial
data word will be ignored unless the received stop bit = 1. If SM2 = 0, then the value of the received stop
bit will be loaded into the RB8 status flag so that it may be processed by the application software.