Maxim Integrated Secure Microcontroller - Manual (Page 2)

Secure Microcontroller User’s Guide
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TABLE OF CONTENTS
1. INTRODUCTION ................................................................................................................. 7
1.1 I MPORTANT N OTICE R EGARDING D ISCONTINUED DS2251T/DS2252T .............................................. 7
1.2 S OFTWARE S ECURITY ..................................................................................................................... 7
1.3 P RODUCT D ESCRIPTION .................................................................................................................. 9
1.4 I NTRODUCTION TO THE DS5250 H IGH -S PEED S ECURE M ICROCONTROLLER ................................... 10
2. SELECTOR GUIDE .......................................................................................................... 12
3. SECURE MICROCONTROLLER ARCHITECTURE ........................................................ 13
3.1 B US O RGANIZATION ...................................................................................................................... 13
3.2 CPU R EGISTERS ........................................................................................................................... 13
4. PROGRAMMER’S GUIDE ................................................................................................ 18
4.1 S ECURE M ICROCONTROLLER M EMORY O RGANIZATION .................................................................. 18
4.1.1 Internal Registers ................................................................................................................................. 19
4.1.2 Program and Data Memory .................................................................................................................. 20
4.2 DS5000 S ERIES M EMORY O RGANIZATION ..................................................................................... 21
4.3 DS5000 M EMORY M AP C ONTROL .................................................................................................. 23
4.4 DS5001/DS5002 M EMORY O RGANIZATION ................................................................................... 24
4.5 DS5001/DS5002 M EMORY -M APPED P ERIPHERALS ....................................................................... 27
4.6 DS5001/DS5002 M EMORY M AP C ONTROL .................................................................................... 28
4.7 L OADING AND R ELOADING P ROGRAM M EMORY .............................................................................. 28
4.8 S PECIAL F UNCTION R EGISTERS ..................................................................................................... 33
4.9 I NSTRUCTION S ET ......................................................................................................................... 48
4.10 A DDRESSING M ODES ................................................................................................................. 48
4.11 P ROGRAM S TATUS F LAGS .......................................................................................................... 50
5. MEMORY INTERCONNECT ............................................................................................ 51
6. LITHIUM/BATTERY BACKUP ......................................................................................... 58
6.1 D ATA R ETENTION .......................................................................................................................... 58
7. POWER MANAGEMENT ................................................................................................. 62
7.1 I DLE M ODE .................................................................................................................................... 62
7.2 S TOP M ODE .................................................................................................................................. 64
7.3 V OLTAGE M ONITORING C IRCUITRY ................................................................................................ 64
7.4 P OWER -F AIL I NTERRUPT ............................................................................................................... 64
7.5 T OTAL P OWER F AILURE ................................................................................................................. 65
7.6 P ARTIAL P OWER F AILURES ............................................................................................................ 66
8. SOFTWARE CONTROL ................................................................................................... 68
8.1 T IMED A CCESS .............................................................................................................................. 68
8.2 W ATCHDOG T IMER ........................................................................................................................ 70
8.3 CRC M EMORY V ERIFICATION ........................................................................................................ 71
8.3.1 Automatic CRC on Power-Up Feature ................................................................................................. 71
9. FIRMWARE SECURITY ................................................................................................... 74
9.1 S ECURITY L OCK ............................................................................................................................ 74
9.2 RAM M EMORY .............................................................................................................................. 75
9.3 E NCRYPTED M EMORY ................................................................................................................... 76
9.4 E NCRYPTION A LGORITHM .............................................................................................................. 78
9.5 E NCRYPTION K EY .......................................................................................................................... 78
9.6 E NCRYPTION K EY S ELECTION AND L OADING .................................................................................. 78
9.7 D UMMY B US A CCESS .................................................................................................................... 79
9.8 O N -C HIP V ECTOR RAM ................................................................................................................. 79
9.9 S ELF -D ESTRUCT I NPUT ................................................................................................................. 80
9.10 M ICROPROBE /D IE T OP C OATING ................................................................................................ 81