Maxim Integrated Secure Microcontroller - Manual (Page 19)

Secure Microcontroller User’s Guide
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4.1.1 Internal Registers
The internal register space is divided into two parts. These are scratchpad registers and SFRs. There are
128 scratchpad registers, commonly referred to as on-chip RAM. The 128 bytes include four 8-byte banks
of working registers (R0–R7). The scratchpad registers are located at register addresses 00–7Fh. This area
is not located in the program or data memory area and is accessed by different instructions. The SFRs are
located between 80h and FFh. SFRs control the on-chip peripherals and memory configurations. Direct
addressing should be used to access the SFR locations. If register-indirect addressing is used,
indeterminate data is returned. Scratchpad registers are discussed immediately below, with SFR
descriptions following later in this section.
The scratchpad registers are general-purpose data storage RAM. They are commonly used for temporary
storage of a small number of variables when high-speed access is needed. Off-chip RAM (MOVX) is
used when the quantity of data is larger than 128 bytes. The scratchpad registers are lithium backed and
are preserved in the absence of power.
The scratchpad area has two additional functions. First, 16 bytes of the scratchpad area are bit
addressable. That is, while each byte has an address of its own, these bits also have individual bit
addresses. Certain instructions operate on bits instead of bytes. Although the addresses appear the same,
the microprocessor can distinguish a bit address from a byte address by the instruction used. A large
number of individual software flags and conditions can be represented using 128 (16 x 8) individually
addressable bits.
A second use of the scratchpad area is for the programmer’s stack. Like the 8051, the secure
microcontroller uses a stack pointer (SP–81h) SFR to direct stack access into the internal registers. The
SP has a default value of 07h. This means that stack storage begins at location 08h. Each PUSH or CALL
instruction increments the SP. Note that while the SP is located in the SFR area, the stack itself is stored
in the scratchpad area.
Figure 4-2 shows the scratchpad register memory map. Programmer’s Note: With
the use of C compilers becoming more frequent, the large memory model should be examined. This
compiler model places the stack in off-chip SRAM. Secure microcontroller-based systems usually have
an abundance of such SRAM compared to ROM based systems. While off-chip stack results in slower
execution time, the stack size becomes virtually unlimited.
The 8051 instruction set allows efficient (single cycle) access to variables when using the working
registers. These are a group of four 8-byte banks of scratchpad RAM. The active working registers are
referred to as R0–R7. They reside between location 00h and 1Fh, depending on which bank is currently
selected. Two bits in the SFR PSW, called R1 (PSW.4) and R0 (PSW.3), are used to determine which is
the active bank. Once selected, all instructions involving R0–R7 are directed to the selected group of 8
bytes. This scheme also allows for a fast context switch by simply changing banks. The following table
shows the operation of the register bank selection.
PSW.4-3; R1–R0
Register Bank Select Used to select an 8-byte bank of registers to be assigned as R0–R7.
R1 R0 BANK STARTING ADDRESS (R0)
0 0 00h
0 1 08h
1 0 10h
1 1 18h