Maxim Integrated Secure Microcontroller - Manual (Page 3)

Secure Microcontroller User’s Guide
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9.11 R ANDOM N UMBER G ENERATOR .................................................................................................. 81
9.12 S ECURITY S UMMARY BY P ART .................................................................................................... 81
9.13 A PPLICATION : A DVANCED S ECURITY T ECHNIQUES ...................................................................... 82
10. RESET CONDITIONS ....................................................................................................... 85
10.1 R ESET S OURCES ....................................................................................................................... 85
10.1.1 Power-On Reset ................................................................................................................................... 87
10.1.2 No-V
LI
Power-On Reset ....................................................................................................................... 88
10.1.3 External Reset ...................................................................................................................................... 88
10.1.4 Watchdog Timer Reset ........................................................................................................................ 88
10.2 M EMORY M AP ............................................................................................................................ 89
10.3 I NTERRUPTS .............................................................................................................................. 90
10.4 T IMERS ...................................................................................................................................... 90
10.5 T RANSIENT V OLTAGE P ROTECTION ............................................................................................. 91
11. INTERRUPTS ................................................................................................................... 92
11.1 I NTERRUPT S OURCES ................................................................................................................ 92
11.2 E XTERNAL I NTERRUPTS .............................................................................................................. 93
11.3 T IMER I NTERRUPTS .................................................................................................................... 93
11.4 S ERIAL P ORT I NTERRUPTS ......................................................................................................... 93
11.5 P OWER -F AIL W ARNING I NTERRUPT ............................................................................................ 94
11.6 S IMULATED I NTERRUPTS ............................................................................................................ 94
11.7 I NTERRUPT P RIORITIES .............................................................................................................. 96
11.8 I NTERRUPT A CKNOWLEDGE ........................................................................................................ 97
12. PARALLEL I/O ................................................................................................................. 99
12.1 O UTPUT F UNCTIONS ................................................................................................................ 102
12.2 I NPUT F UNCTION ...................................................................................................................... 103
12.3 R EAD -M ODIFY -W RITE I NSTRUCTIONS ....................................................................................... 104
12.4 R EPROGRAMMABLE P ERIPHERAL C ONTROLLER (RPC) ............................................................. 104
12.5 RPC I NTERRUPTS .................................................................................................................... 106
12.6 RPC P ROTOCOL ...................................................................................................................... 107
12.7 DMA O PERATION ..................................................................................................................... 107
13. PROGRAMMABLE TIMERS .......................................................................................... 109
13.1 F UNCTIONAL D ESCRIPTION ....................................................................................................... 109
13.2 M ODE 0 ................................................................................................................................... 111
13.3 M ODE 1 ................................................................................................................................... 111
13.4 M ODE 2 ................................................................................................................................... 112
13.5 M ODE 3 ................................................................................................................................... 114
14. SERIAL I/O ..................................................................................................................... 115
14.1 F UNCTION D ESCRIPTION .......................................................................................................... 115
14.2 B AUD R ATE G ENERATION ......................................................................................................... 118
14.3 S YNCHRONOUS O PERATION (M ODE 0) ...................................................................................... 119
14.4 A SYNCHRONOUS O PERATION ................................................................................................... 120
15. CPU TIMING ................................................................................................................... 130
15.1 O SCILLATOR ............................................................................................................................ 130
15.2 I NSTRUCTION T IMING ............................................................................................................... 131
15.3 E XPANDED P ROGRAM M EMORY T IMING .................................................................................... 132
15.4 E XPANDED D ATA M EMORY T IMING ........................................................................................... 135
16. PROGRAM LOADING .................................................................................................... 137
16.1 I NVOKING THE B OOTSTRAP L OADER ......................................................................................... 137
16.2 I NVOKING THE B OOTSTRAP L OADER ON DS5000 S ERIES D EVICES ............................................ 138
16.3 I NVOKING THE B OOTSTRAP L OADER ON DS5001/DS5002 S ERIES D EVICES .............................. 138
16.4 E XITING THE L OADER ............................................................................................................... 139
16.5 S ERIAL P ROGRAM L OAD M ODE ................................................................................................. 141